Silicon Labs /EFR32FG23B020F512IM48 /SMU_S /PPUSATD0

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Interpret as PPUSATD0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EMU)EMU 0 (CMU)CMU 0 (HFRCO0)HFRCO0 0 (FSRCO)FSRCO 0 (DPLL0)DPLL0 0 (LFXO)LFXO 0 (LFRCO)LFRCO 0 (ULFRCO)ULFRCO 0 (MSC)MSC 0 (ICACHE0)ICACHE0 0 (PRS)PRS 0 (GPIO)GPIO 0 (LDMA)LDMA 0 (LDMAXBAR)LDMAXBAR 0 (TIMER0)TIMER0 0 (TIMER1)TIMER1 0 (TIMER2)TIMER2 0 (TIMER3)TIMER3 0 (TIMER4)TIMER4 0 (USART0)USART0 0 (BURTC)BURTC 0 (I2C1)I2C1 0 (CHIPTESTCTRL)CHIPTESTCTRL 0 (SYSCFGCFGNS)SYSCFGCFGNS 0 (SYSCFG)SYSCFG 0 (BURAM)BURAM 0 (GPCRC)GPCRC 0 (DCDC)DCDC 0 (HOSTMAILBOX)HOSTMAILBOX 0 (EUSART1)EUSART1 0 (EUSART2)EUSART2

Description

Set peripheral bits to 1 to mark as secure access only

Fields

EMU

EMU Secure Access

CMU

CMU Secure Access

HFRCO0

HFRCO0 Secure Access

FSRCO

FSRCO Secure Access

DPLL0

DPLL0 Secure Access

LFXO

LFXO Secure Access

LFRCO

LFRCO Secure Access

ULFRCO

ULFRCO Secure Access

MSC

MSC Secure Access

ICACHE0

ICACHE0 Secure Access

PRS

PRS Secure Access

GPIO

GPIO Secure Access

LDMA

LDMA Secure Access

LDMAXBAR

LDMAXBAR Secure Access

TIMER0

TIMER0 Secure Access

TIMER1

TIMER1 Secure Access

TIMER2

TIMER2 Secure Access

TIMER3

TIMER3 Secure Access

TIMER4

TIMER4 Secure Access

USART0

USART0 Secure Access

BURTC

BURTC Secure Access

I2C1

I2C1 Secure Access

CHIPTESTCTRL

CHIPTESTCTRL Secure Access

SYSCFGCFGNS

SYSCFGCFGNS Secure Access

SYSCFG

SYSCFG Secure Access

BURAM

BURAM Secure Access

GPCRC

GPCRC Secure Access

DCDC

DCDC Secure Access

HOSTMAILBOX

HOSTMAILBOX Secure Access

EUSART1

EUSART1 Secure Access

EUSART2

EUSART2 Secure Access

Links

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